1. Field of the Invention
Embodiments of the present invention relate to methods and compositions for removing a conductive material from a substrate.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed using sequential material deposition and material removal techniques on a substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarization or “polishing” is a process in which material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material, removing undesired surface topography, and surface defects, such as surface roughness, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent photolithography and other semiconductor manufacturing processes.
It is extremely difficult to planarize a metal surface, particularly a tungsten surface, as by chemical mechanical polishing (CMP), which planarizes a layer by chemical activity as well as mechanical activity, of a damascene inlay as shown in FIGS. 1A and 1B, with a high degree of surface planarity. A damascene inlay formation process may include etching feature definitions in an interlayer dielectric, such as a silicon oxide layer, depositing a barrier layer in the feature definitions and on a surface of the substrate, and depositing a thick layer of conductive material, such as tungsten, on the barrier layer and substrate surface. The tungsten material is chemical mechanical polished to expose the barrier layer and the tungsten filled feature definitions or “plugs.” However, chemical mechanical polishing of the tungsten material to remove excess tungsten material above the substrate surface often results in topographical defects, such as dishing and erosion, that may affect subsequent processing of the substrate.
Dishing occurs when a portion of the surface of the inlaid metal of the interconnection formed in the feature definitions in the interlayer dielectric is excessively polished, resulting in one or more concave depressions, which may be referred to as concavities or recesses. Referring to FIG. 1A, a damascene inlay of conductive lines 11 and 12 are formed by depositing a metal, such as tungsten (W) or a tungsten alloy, in a damascene opening formed in an interlayer dielectric 10, for example, silicon dioxide. While not shown, a barrier layer of a suitable material such as titanium and/or titanium nitride for tungsten may be deposited between the interlayer dielectric 10 and the inlaid metal 12. Subsequent to planarization, a portion of the inlaid metal 12 may be depressed by an amount D, referred to as the amount of dishing. Dishing is more likely to occur in wider or less dense features on a substrate surface.
Conventional planarization techniques also sometimes result in erosion, characterized by excessive polishing of the layer not targeted for removal, such as a dielectric layer surrounding a filled feature definition. Referring to FIG. 1B, a tungsten fill 21 formed in a dense array of feature definitions 22 are inlaid in interlayer dielectric 20. Polishing the substrate may result in loss, or erosion E, of the dielectric 20 between the tungsten filled feature definitions. Erosion is observed to occur near narrower or more dense features formed in the substrate surface. Modifying conventional tungsten CMP polishing techniques has resulted in less than desirable polishing rates and results than is commercially acceptable.
Therefore, there is a need for methods and compositions for removing conductive material, such as excess tungsten material, from a substrate that minimizes the formation of topographical defects to the substrate during planarization.